Signal integrity is rapidly becoming one of the important issues in IC designs, especially in very large scale integration (VLSI) physical designs. As the chip size and performance are increasing, the process feature size is reducing. This can result in a higher parasitic induced capacitance on the signal lines which can result in having a very strong impact on the design functionality. Such noise may reduce performance or even introduce logic failures into the IC system.
In IC designs, filler metal polygons (electrically inactive areas) are added to chips in order to maintain an even distribution of metal density across a chip, which reduces the potential for defects on the chip due to uneven chemical-mechanical polishing (CMP) during the chip manufacturing process. Having a certain percentage of coverage for metal has been a general requirement for foundries. Typically, metal density is maintained in the range of about 20% to 80%.
In order to meet the metal coverage requirements, chip designers generally add filler metal polygons on each metal layer in a chip without giving any consideration to coupling capacitance between metal routes and added filler metal polygons. Exemplary metal routes include power routes, clock routes, and signal routes. Typically, the size of the filler metal polygons is about 3 microns×3 microns in size. The added filler metal polygons that violate minimum spacing requirements (between the added filler metal polygon and the metal route) are removed and then checked for metal density requirements. If the metal density requirements are not met, then the above process is repeated until the metal density requirements are met. In general, the above process can become very iterative and time consuming.
In addition, the above technique often leaves the added filler metal polygons too close to the metal routes due to the effort to increase the metal density. This can lead to increased parasitic capacitance, i.e., coupling capacitance between the metal routes and the added filler metal polygons. This in turn, can affect the performance of the chip, such as reducing the frequency of operation of the chip or can affect the functionality of the design. In some instances, the frequency degradation can be as much as 10%. Thus, in the deep sub-micron range, the characteristics of the metal routes (interconnect) and the filler metal polygons can significantly dominate the overall performance of a chip.